// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    : phy_config.v
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/10/12
// Version      :  V 1.0 
// 
//Abstract      :  
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 
//  
// *********************************************************************
// `include "top_define.v"
//`include "common_header.verilog"
//`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"
//`include "host_pin_if.svh"  // HOST interface
//`include "dut_interfaces.svh"
// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/10fs 

// *******************
// DESCRIPTION
// *******************
// 
// 
//*******************
//DEFINE(s)
//*******************

//*******************
//DEFINE PARAMETER
//*******************
//Parameter(s) 

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS


//WIRES


//*********************
//INSTANTCE MODULE
//*********************

//*********************
//MAIN CODE
//*********************
// assign bs_rx_bigswing         =     1'd1    ; 
// assign bs_tx_lowswing         =     1'd0    ; 
// assign lanex_rx2tx_par_lb_en  =     1'd0    ; 
// assign lanex_tx2rx_ser_lb_en  =     1'd0    ; 
// assign mplla_bandwidth        =     11'd111 ; 
// assign mplla_div10_clk_en     =     1'd1    ; 
// assign mplla_div16p5_clk_en   =     1'd0    ; 
// assign mplla_div8_clk_en      =     1'd0    ; 
// assign mplla_div_clk_en       =     1'd1    ; 
// assign mplla_div_multiplier   =     7'd10   ; 
// assign mplla_force_en         =     1'd0    ; 
// assign mplla_fracn_ctrl       =     9'd0    ; 
// assign mplla_init_cal_disable =     1'd0    ; 
// assign mplla_multiplier       =     8'd33   ; 
// assign mplla_ssc_clk_sel      =     3'd0    ; 
// assign mplla_ssc_en           =     1'd0    ; 
// assign mplla_ssc_range        =     3'd0    ;
// assign mpllb_bandwidth        =     11'd122 ; 
// assign mpllb_div10_clk_en     =     1'd1    ; 
// assign mpllb_div8_clk_en      =     1'd0    ; 
// assign mpllb_div_clk_en       =     1'd0    ; 
// assign mpllb_div_multiplier   =     7'd0    ; 
// assign mpllb_force_en         =     1'd0    ; 
// assign mpllb_fracn_ctrl       =     9'd0    ; 
// assign mpllb_init_cal_disable =     1'd0    ; 
// assign mpllb_multiplier       =     8'd40   ; 
// assign mpllb_ssc_clk_sel      =     3'd0    ; 
// assign mpllb_ssc_en           =     1'd0    ; 
// assign mpllb_ssc_range        =     3'd0    ; 

// assign ref_clk_div2_en        =     1'd0    ; 
// assign ref_clk_mplla_div2_en  =     1'd1    ; 
// assign ref_clk_mpllb_div2_en  =     1'd1    ; 
// assign ref_range              =     3'd6    ; 
// assign rxx_adapt_afe_en       =     (lane_40Geth_ena)? 1'd1:1'd0; 
// assign rxx_adapt_cont         =     1'd1    ; //?
// assign rxx_adapt_dfe_en       =     (lane_40Geth_ena)? 1'd1:1'd0; 
// assign rxx_adapt_req          =     1'd0    ; 
// assign rxx_align_en           =     1'd0    ; //??
// assign rxx_cdr_ssc_en         =     1'd0    ; 
// assign rxx_cdr_track_en       =     1'd1    ; 
// assign rxx_cdr_vco_lowfreq    =     1'd1    ; 
// assign rxx_clk_shift          =     1'd0    ; 
// assign rxx_data_en            =     1'd1    ; 
// assign rxx_disable            =     1'd0    ; 
// assign rxx_div16p5_clk_en     =     (lane_40Geth_ena)? 1'd1:1'd0; 
// assign rxx_eq_att_lvl         =     3'd0    ; 
// assign rxx_eq_ctle_boost      =     (lane_40Geth_ena)? 5'd10:5'd6; 
// assign rxx_eq_ctle_pole       =     (lane_40Geth_ena)? 3'd2:3'd0; 
// assign rxx_eq_dfe_tap1        =     8'd0    ; 
// assign rxx_eq_vga1_gain       =     4'd7    ; 
// assign rxx_eq_vga2_gain       =     4'd7    ; 
// assign rxx_invert             =     1'd0    ; 
// assign rxx_los_lfps_en        =     1'd0    ; 
// assign rxx_los_threshold      =     3'd3    ; 
// assign rxx_lpd                =     1'd0    ; 
// assign rxx_offcan_cont        =     1'd1    ; 
// assign rxx_pstate             =     2'd0    ; 
// assign rxx_rate               =     (lane_40Geth_ena)? 2'd2:2'd0; 
// assign rxx_ref_ld_val         =     (lane_40Geth_ena)? 6'd41   :6'd34; 
// assign rxx_term_acdc          =     1'd1    ; 
// assign rxx_term_en            =     1'd1    ; 
// assign rxx_vco_ld_val         =     (lane_40Geth_ena)? 13'd1353:13'd1360; 
// assign rxx_width              =     2'd3; 
// assign txx_beacon_en          =     1'd0    ; 
// assign txx_data_en            =     1'd1    ; 
// assign txx_detrx_req          =     1'd0    ; 
// assign txx_disable            =     1'd0    ; 
// assign txx_eq_main            =     (lane_40Geth_ena)? 6'd40:6'd32; 
// assign txx_eq_post            =     (lane_40Geth_ena)? 6'd0:6'd32; 
// assign txx_eq_pre             =     (lane_40Geth_ena)? 6'd0:6'd0; 
// assign txx_iboost_lvl         =     4'd15   ; 
// assign txx_invert             =     1'd0    ; 
// assign txx_lpd                =     1'd0    ; 
// assign txx_mpll_en            =     1'd0    ; 
// assign txx_mpllb_sel          =     (lane_40Geth_ena)? 1'd0:1'd1; 
// assign txx_pstate             =     2'd0    ; 
// assign txx_rate               =     (lane_40Geth_ena)? 2'd0:2'd2; 
// assign txx_vboost_en          =     1'd1; 
// assign txx_width              =     2'd3; 
// assign tx_vboost_lvl          =     3'd5    ; 
// assign rx_vref_ctrl           =     5'd15   ; 

// assign tx0_clk = (lane_40Geth_ena)? mplla_word_clk:mpllb_qword_clk;
// assign tx0_clk_rdy = (lane_40Geth_ena)? mplla_state:mpllb_state;

// assign tx1_clk = (lane_40Geth_ena)? mplla_word_clk:mpllb_qword_clk;
// assign tx1_clk_rdy = (lane_40Geth_ena)? mplla_state:mpllb_state;

// assign tx2_clk = (lane_40Geth_ena)? mplla_word_clk:mpllb_qword_clk;
// assign tx2_clk_rdy = (lane_40Geth_ena)? mplla_state:mpllb_state;

// assign tx3_clk = (lane_40Geth_ena)? mplla_word_clk:mpllb_qword_clk;
// assign tx3_clk_rdy = (lane_40Geth_ena)? mplla_state:mpllb_state;

// assign tx0_master_mplla_state = mplla_state;
// assign tx0_master_mpllb_state = mpllb_state;

// assign tx1_master_mplla_state = mplla_state;
// assign tx1_master_mpllb_state = mpllb_state;

// assign tx2_master_mplla_state = mplla_state;
// assign tx2_master_mpllb_state = mpllb_state;

// assign tx3_master_mplla_state = mplla_state;
// assign tx3_master_mpllb_state = mpllb_state;

